Microprogram address dualing

Details Microprogram address dualing Microprogram address dualing

G - Physics

06

F

354/230.71

G06F 13/00 (2006.01) G06F 9/26 (2006.01)

Patent

CA 1093214

ABSTRACT A method and an apparatus for improving the speed of executing instructions and reducing the microprogram memory requirements in a conventional digital computer system by utilizing a predetermined bit position to perform a dual function. The method or apparatus incor- porates the use of a predetermined bit position (i.e., dual bit) in a microinstruction word which when set to a binary one causes the microinstruction execution sequence to branch to an address which is comprised of the current address incremented by a predetermined fixed constant other than one. When the dual bit is set to zero, the microinstruction execution sequence does not branch. By the use of a dual bit apparatus, a full branch can be taken (as opposed to an increment to a next microword) while at the same time utilizing a full function micro- instruction type instead of the limited function micro- instruction type such as a branch microinstruction which requires a complete ROM cycle. Hence, a microprogram for carrying out a specific function does not require con- tiguous ROM space, yet does not receive a conventional branch order which would penalize speed and throughput. -1-

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