Minimal delay rate-change circuits

Details Minimal delay rate-change circuits Minimal delay rate-change circuits

H - Electricity

04

J

363/15, 354/235

H04J 3/02 (2006.01) H04L 25/05 (2006.01)

Patent

CA 1164112

- 21 - ABSTRACT "Improvements in or relating to Rate-Change Circuits and Methods" Rate-change circuits for transmitting data samples partitioned into blocks comprise, for example, an arrangement of storage devices (101 to 105) between input (100) and output (600) with individual storage lengths increasing according to a geometric progression, storage means (106) arranged between input and output to store all but one of the remaining samples unallocated to the storage devices, input clocking means (201 to 207) to route input samples to appropriate storage devices or means, and output clocking means (501 to 507) to gate the accumulated samples to the output. The topological arrangement relies on the ability of a storage device to shift out while the next lower size storage device is being loaded.

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