Minimization of interfacial resistance across thermoelectric...

H - Electricity – 01 – L

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H01L 21/4763 (2006.01)

Patent

CA 2622981

A coating architecture (106, 206, 306) minimizing interfacial resistance across an interface (100, 200, 300) of a metal (104, 204, 304) and a semiconductor including at least two layers (108, 110, 112, 208, 210, 212, 306) intermediate the metal (104, 204, 304) and the semiconductor.

La présente invention concerne une structure de revêtement (106, 206, 306) destinée à minimiser la résistance intefaciale dans l~interface (100, 200, 300) d~un métal (104, 204, 304) ainsi qu~un semiconducteur présentant au moins deux couches (108, 110, 112, 208, 210, 212, 306) entre le métal (104, 204, 304) et le semiconducteur.

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