G - Physics – 06 – F
Patent
G - Physics
06
F
354/230.8
G06F 9/38 (2006.01) G06F 9/45 (2006.01)
Patent
CA 2031112
A compiler module is disclosed which minimizes pipeline breaks by reordering object code instructions to avoid conflicts between closely grouped instructions to the extent possible. Representation of each object code instruction in a small sequential group is temporarily held in a buffer and is assigned a pair of Attribute Words. Potential conflicts which a newly called instruction may have with those instructions already in the buffer are ascertained by logically AND-ing its Attribute Words with those of the other instructions and examining the result. If a conflict does exist, an attempt is made to resolve it by determining if the conflicting instruction already in the buffer can be moved ahead of one or more other instructions in the buffer such that the conflict is eliminated or minimized. This procedure involves a comparison of the Attribute Words of the candidate instruction to be moved, Im, with the other instructions in the buffer. If movement of the conflicting instruction is possible and will resolve or minimize the conflict, the instructions in the buffer are reordered as appropriate.
Intel Corporation
Smart & Biggar
LandOfFree
Minimizing hardware pipeline breaks using software... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Minimizing hardware pipeline breaks using software..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Minimizing hardware pipeline breaks using software... will most certainly appreciate the feedback.
Profile ID: LFCA-PAI-O-1430103