Minimizing plating stub reflections in a chip package using...

Details Minimizing plating stub reflections in a chip package using... Minimizing plating stub reflections in a chip package using...

H - Electricity

01

L

H01L 23/31 (2006.01) H01L 23/498 (2006.01) H01L 23/50 (2006.01) H05K 1/14 (2006.01)

Patent

CA 2669618

Embodiments of the present invention are directed to shifting the resonant frequency in a high-frequency chip package away from an operational frequency by connecting a capacitance between an open-ended plating stub and ground. One embodiment provides a multi-layer substrate for interfacing a chip with a printed circuit board. A first outer layer provides a chip mounting location. A signal interconnect is spaced from the chip mounting location, and a signal trace extends from near the chip mounting location to the signal interconnect. A chip mounted at the chip mounting location may be connected to the signal trace by wirebonding. A plating stub extends from the signal interconnect, such as to a periphery of the substrate. A capacitor is used to capacitively couple the plating stub to a ground layer.

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