Minimum pitch mosfet decoder circuit configuration

Details Minimum pitch mosfet decoder circuit configuration Minimum pitch mosfet decoder circuit configuration

G - Physics

11

C

352/82.3

G11C 11/40 (2006.01) G11C 8/10 (2006.01) G11C 8/12 (2006.01) G11C 8/14 (2006.01) G11C 17/12 (2006.01) H03M 7/00 (2006.01)

Patent

CA 1058754

MINIMUM PITCH MOSFET DECODER CIRCUIT CONFIGURATION ABSTRACT OF THE DISCLOSURE: MOSFET decoder circuit configuration for enhancing read/only storage memory densities by providing decoded output lines on a narrower pitch than conventional decoder circuits, thereby, increasing the number of decoded lines of the conventional decoder. In addition the number of conventional decoder circuits required are reduced by a binary factor, thereby decreasing power requirements. Decoded line capability is increased by means of properly addressed array select devices whereby the number of array select devices required is equal to the particular binary factor utilized. For particular physical layout ground rules utilized in fabrication of an integrated decoder of the instant invention, the binary factor is chosen so that the decoder pitch is equal to the read/only storage memory pitch in order to obtain maximum chip density.

239231

Affiliated with

Also associated with

Rating

Minimum pitch mosfet decoder circuit configuration does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Minimum pitch mosfet decoder circuit configuration, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Minimum pitch mosfet decoder circuit configuration will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-740688