Mitigating single event upset phenomenon in semiconductor...

Details Mitigating single event upset phenomenon in semiconductor... Mitigating single event upset phenomenon in semiconductor...

H - Electricity

03

K

H03K 19/00 (2006.01) H01L 23/552 (2006.01) H03K 19/003 (2006.01)

Patent

CA 2348200

A circuit and method to mitigate the effects of single event upset phenomenon. The circuit includes a logic gate connected to provide a fault output only when inputs to the logic gate are all in the fault state. The method includes comparing the outputs of circuits susceptible to single event upset phenomenon and providing a fault output only when all circuits are in a fault condition.

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