Mnos fet memory retention characterization test circuit

Details Mnos fet memory retention characterization test circuit Mnos fet memory retention characterization test circuit

G - Physics

11

C

356/117, 352/82.

G11C 11/40 (2006.01) G11C 7/00 (2006.01) G11C 11/34 (2006.01) G11C 16/04 (2006.01) G11C 29/50 (2006.01)

Patent

CA 1106077

ABSTRACT OF THE DISCLOSURE A method and sense latch circuit are described for determining the memory retention characteristics of differen- tially sensed metal nitride oxide semiconductor field effect transistor (MNOS FET) memory cells and arrays made up of such cells. The method involves substitution of one differential comparator input with a known reference voltage (VR) for de- termining the analog voltage threshold levels of the memory cells. The sense latch circuit, which can be fabricated as an integrated circuit, is responsively coupled to control inputs so that it can be operated in either a read or memory retention interrogation mode. The determination of the analog threshold levels of each cell of an array at given times permits the determination of the array's memory window (i.e., memory retention characteristics).

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