Mnos fet memory retention characterization test circuit with...

Details Mnos fet memory retention characterization test circuit with... Mnos fet memory retention characterization test circuit with...

G - Physics

11

C

356/117, 352/82.

G11C 11/40 (2006.01) G11C 11/34 (2006.01) G11C 16/04 (2006.01)

Patent

CA 1108308

ABSTRACT OF THE DISCLOSURE An improved sense latch circuit for differentially sensing an MNOS memory FET's voltage thresholds, selectively operable in either a memory retention or read interrogation mode with enhanced sensitivity and improved power con- servation. The improvement consisting of the additional cross coupling of each of the latch outputs to a respective plurality of MOS FETs coupled in series with each of the MNOS FET inputs, which cross coupling reduces extraneous current paths and increases the switching sensitivity of the sense latch circuit.

308213

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