Mnos storage cell

Details Mnos storage cell Mnos storage cell

G - Physics

11

C

352/82.3

G11C 11/34 (2006.01) H01L 29/792 (2006.01)

Patent

CA 1161959

ABSTRACT OF THE DISCLOSURE The invention relates to a MNOS memory cell arrangement in VLSI (very large scale integration) technology comprised of a multi-layer gate insulating layer covering a surface of a semiconductor body in the region between the source and drain zones. In order to avoid breakdowns at the source and drain zone edges before an erasure voltage is attained, the gate elec- trode is split into two electrodes, which can be operated in different ways and which are superimposed one upon another. These gate electrodes are connec- ted via self-aligned, overlapped contacts. This arrangement avoids "short channel erasure", even in the case of VLSI technology. The invention can be applied as required to MNOS EEPROM memory devices.

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