Moat router for integrated circuits

Details Moat router for integrated circuits Moat router for integrated circuits

G - Physics

06

F

356/30

G06F 17/50 (2006.01)

Patent

CA 1280220

MOAT ROUTER FOR INTEGRATED CIRCUITS Abstract of the Disclosure A method of specification of the routing of signal and planar power nets between terminals of a core module and pads in an array of pads surrounding the core module. The method identifies proximity terminals and cyclic constraints and then routes the signal nets and power nets in separate moat rings that are concentric with the core module. The proximity terminals and any pads involved in cyclic constraints are routed in respective proximity and cyclic moat rings, adjacent the core module and pad array, respectively. Finally, the resulting moat signal nets are promoted within the signal to the next most outwardly adjacent, unoccupied concentric tracks, and then sections of the proximity, signal, power, and cyclic rings are collapsed to the next most radially inward, unoccu- pied concentric tracks. In a further step, the method of the present invention can route each of the possible orientations of the core module with respect to the array of pads, thereby determining the minimum possible chip area for the desired integrated circuit.

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