G - Physics – 11 – C
Patent
G - Physics
11
C
G11C 16/02 (2006.01) G11C 16/06 (2006.01)
Patent
CA 2704894
The flash and SRAM memory (112, 113) are embedded within an application specific integrated circuit (ASIC) to provide improved access times and also reduce over all power consumption of a mobile telephone employing the ASIC. The flash memory system (112) includes a flash memory array (130) configured to provide a set of individual flash macros and a flash memory controller (132) for accessing the flash macros. The flash memory controller includes a read while writing unit (144, 146) for writing to one of the flash macros while simultaneously reading from another of the flash macros. The flash memory controller also includes programmable wait state registers (138) and a password register (140) providing a separate password for different portions of the flash memory array. A memory swap unit (149) is provided for swapping high and low memory subsequent to completion of operations performed by the boot loader. Method and apparatus implementations are disclosed.
Elhusseini Jalal
Jha Sanjay
Khan Safi
Simmonds Stephen
Yu Nicholas K.
Qualcomm Incorporated
Smart & Biggar
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