Modular implementation for a parallelized key equation...

Details Modular implementation for a parallelized key equation... Modular implementation for a parallelized key equation...

H - Electricity

03

M

H03M 13/00 (2006.01) H03M 13/15 (2006.01)

Patent

CA 2057666

SA9-91-003 Abstract of the Disclosure Apparatus and method for implementing a parallelized algorithm for solving the key equation for the decoding of a linear algebraic code. A computational loop has one branching condition that branches into two straight-line loops. One of these executes three multiplication operations and the other executes five multiplication operations, 2t iterations of these two loops being required to decode t symbols in error. These loops are coupled such that during each successive 2t iterations, four multiplication operations are executed simultaneously in pairs, the fifth multiplication operation in said other loop being paired with a multiplication operation in the next iteration of said one loop. During one of the paired multiplication operations an inverse table look up operation is executed, and during another of the multiplication operations an addition operation is executed.

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