G - Physics – 11 – C
Patent
G - Physics
11
C
352/82.3
G11C 11/40 (2006.01)
Patent
CA 1063242
Abstract of the disclosure A dynamic MOS one transistor cell memory having a plurality of divided bit lines and a corresponding plurality of flip-flop sense amplifiers. Each bit line being divided into two electrically balanced parts which run adjacent and parallel to each other, and extend from the input/output nodes of their corresponding flip-flop sense amplifier to a balanced data access bus. The balanced data access bus being connected, in turn, to balanced data access, or read/ write, circuitry. By virtue of the connection of balanced bit, and bus lines, and balanced data access circuitry, to each flip-flop sense amplifier, the probability of reading errors due to circuit imbalances at the input/output nodes of the flip-flops is greatly lessened. The direct connection, from the read/write circuitry to both parts of each bit line, arising from this arrangement obviates the need to enable a flip-flop sense amplifier in order to perform a writing operation, and permits a read-modify-write operation with flip-flop sense amplifiers designed with dynamic loads. - i -
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