G - Physics – 11 – C
Patent
G - Physics
11
C
352/82.3
G11C 11/40 (2006.01) G11C 11/404 (2006.01)
Patent
CA 1037606
Abstract of the Disclosure A dynamic, random access, MOS transistor memory (RAM), having single transistor storage elements and a flip-flop circuit associated with each row of storage elements. The flip-flop circuits serving to reduce the stray capacitances of the bit lines, so as to permit more distance data signal levels thereon during the reading operation, and in addition provide the necessary energy required to rewrite data destroyed by the reading operation. A common mode potential is established at the input/output nodes of each flip-flop, during the quiescent period of the memory, by connecting the input/output nodes of each flip-flop through respective MOS transistor switches to a source of electrical potential. The gate elect- rodes of the MOS transistors, which connect the input/output nodes of the flip-flops to the source of electrical potential, are enabled by a signal having a potential greater than the potential appearing at the aforementioned source of electrical potential, so as to establish low impedance connections between the input/output nodes and the source of electrical potential. These low impedance connections serve to establish substant- ially equal potential levels, at the input/output node, of the flip-flops, which are substantially independent of transistor parameter variations and unaffected by undesired noise signals. - i -
232144
Foss Richard C.
Harland Robert F.
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