Mos transistor output circuits using pmos transistors

Details Mos transistor output circuits using pmos transistors Mos transistor output circuits using pmos transistors

H - Electricity

03

K

H03K 19/0185 (2006.01) H03K 19/0175 (2006.01)

Patent

CA 2337278

A signal voltage converter converts a 0V to -5V input signal to a +5V to 0V output signal using PMOS transistors for both pull-up and pull-down of the output. Bipolar transistor level shifters and PMOS current mirrors are used to control the pull-up and pull-down transistors in conjunction with a clamp circuit. Output signal transitions are matched for both transition directions to reduce signal timing distortion, and this can be further enhanced by an optional circuit for supplying a controlled current for the clamp circuit.

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