G - Physics – 11 – C
Patent
G - Physics
11
C
352/82
G11C 11/40 (2006.01) G11C 11/411 (2006.01) G11C 11/416 (2006.01) H01L 27/02 (2006.01)
Patent
CA 1236574
ABSTRACT Semiconductor integrated word organised store comprising a two- dimensional array of bistable storage cells linked by orthogonal word lines and pairs of bit lines. Each cell consists of two cross-coupled MTL gates having a structure providing a vertical inverting base transistor and two complementary lateral injector transistors. A cell is driven by read/write logic connected to the word lines and bit lines only. To read the contents of a word from the array, read logic drives the read injectors of the cells constituting the word at a high injector current level and the read injectors of all other cells at a low injector current level. To select a word for writing, the read logic drives the read injectors of the cells comprising the word at a low injector current level and all other cells at a high injector current level. The contents of the selected word may then be charged by dif- ferentially driving the cell write injectors over the bit lines. Output multiplexing of cells storing corresponding bit positions in the words is achieved simply by connecting the cell outputs together (dot ANDing). Logical output discrimination and interfacing is achieved by comparing the multiplexed output current with a threshold current. If the output current is less than the threshold the cell is storing a logical ONE. If the output current is greater than the threshold the cell is storing a logical ZERO.
481526
Thomas Vincent P.
West Roderick M.
Woodley John P.
International Business Machines Corporation
Saunders Raymond H.
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