Multi-chip data detector implementation for symmetric...

Details Multi-chip data detector implementation for symmetric... Multi-chip data detector implementation for symmetric...

H - Electricity

04

L

H04L 27/22 (2006.01) H04L 27/233 (2006.01)

Patent

CA 2311021

A multi-chip data decoder implemented for symmetric differential phase shift keying (SDPSK) or symmetric differential quadriphase shift keying (SDQPSK) modulation formats which uses multiple-chip observation intervals to improve performance over conventional symbol-to-symbol differential detection. Input phases .PHI.k, .PHI.k-1 .PHI.k- 2,and.PHI.k-3 are detected by comparing a received vector of data bits and parity bits, which contains phase transition information over multiple chips, to the set of ideal vectors of data bits and parity bits, which contain all phase transition possibilities over that set of chips in a noiseless environment. The multi-chip data detector for decoding incoming modulated data comprises a phase-difference encoder (10, 100) arranged to encode phase-differences .PHI.k- 2 - .PHI.k-3 .PHI.k-1 - .PHI.k-2 .PHI.k-.PHI.k-1-.PHI.k-.PHI.k-2 .PHI.k-1-.PHI.k-3 and .PHI.k-.PHI.k-3 of the incoming modulated data during a multiple-chip observation interval to produce a received vector of a predetermined number of data bits and parity bits; a decoder (20, 200) arranged to decode the received vector to produce multiple bit decisions by mapping the received vector with a set of ideal vectors; and a majority voter (30, 300) arranged to choose a bit estimate from the multiple bit decisions by way of a majority rule to produce a final detected symbol from the incoming modulated data during the multiple-chip observation interval. The multi-chip data detection technique performs multiple-chip comparisons in an efficient manner, providing a significant performance and implementation improvement over conventional symbol-to-symbol differential detection while realizing design gate savings of up to 90%.

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