Multi-cpu interlock

Details Multi-cpu interlock Multi-cpu interlock

G - Physics

06

F

354/234

G06F 15/16 (2006.01) H04L 29/00 (2006.01)

Patent

CA 1288525

ABSTRACT A multi-CPU interlock mechanism is disclosed which permits the simultaneous servicing of two or more CPUs when an input/output (I/O) order is issued from each of these CPUs. When two CPUs issue simultaneous input/output orders which typically have function code pairs, such as for example, FC=09/OD, each of these orders being individual orders but with the second OD order having no source identifier, the invention permits both of these CPUs to be serviced by causing a negative acknowledge (NAK) signal to be issued to the second CPU until the first IOLD orders have been serviced, thus preventing ambiguous cycles and an inability of the CPUs to be serviced.

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