Multi-emitter bicmos logic circuit family with superior...

Details Multi-emitter bicmos logic circuit family with superior... Multi-emitter bicmos logic circuit family with superior...

H - Electricity

03

K

328/128

H03K 19/094 (2006.01) H03K 19/01 (2006.01)

Patent

CA 1313401

A MULTI-EMITTER BICMOS LOGIC CIRCUIT FAMILY WITH SUPERIOR PERFORMANCE Abstract of the Disclosure A multi emitter multi input BICMOS NAND circuit is provided wherein an output node OUT connected to an output terminal is coupled between pull up and pull down blocks. According to one embodiment of the present invention, the pull up block is comprised of a plurality of identical basic cells, each comprised of a CMOS inverter driving an NPM pull up transistor mounted as an emitter follower. Logic signals are applied on the inputs of the inverters, and the inverted signal (A31, A32) is available at the emitter of the emitter follower which corresponds to the output of the cell. All outputs are tied altogether to perform an OR function and are connected to said output terminal to have a multi emitter like circuit. The pull down block in this embodiment is comprised of two FETs serially connected between said output node OUT and a discharge device such as a feedback NFET, the gate of which is connected to said output node OUT. These two FETs are for driving a NPM pull down transistor, the collector of which is also connected to the output node OUT. The invention includes a number of other embodiments including a feedback inverter embodiment, a parasitic node discharge embodiment, and a BIFET latch embodiment. FR9-87-016

584358

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