Multi-level interconnection cmos devices including sog

Details Multi-level interconnection cmos devices including sog Multi-level interconnection cmos devices including sog

H - Electricity

01

L

356/177

H01L 21/465 (2006.01) H01L 21/316 (2006.01) H01L 21/768 (2006.01) H01L 21/314 (2006.01)

Patent

CA 2026605

A method of manufacturing a semiconductor wafer, comprises performing a first metallization to deposit a first layer of interconnect material on a substrate, etching the interconnect material to form interconnect tracks, depositing a first low temperature dielectric layer over the interconnect tracks, planarizing the first low temperature dielectric layer with quasi-inorganic or inorganic spin-on glass by a non-etchback process, depositing a second low temperature dielectric layer over the spin-on glass, etching via holes through the dielectric and spin-on galss layers to reach the tracks of the first interconnect layer, performing an in-situ desorption of physically and chemically bonded water vapour in a dry environment at a temperature of at least 400°C and not more than 550°C for a time sufficient to obtain a negligible desorption rate, the temperature exceeding by at least 25°C the temperature to which the surface of the wafer will be exposed during a subsequent metallization step, and performing the subsequent metallization step to deposit a second interconnect layer extending through the via holes to the first interconnect tracks without re-exposure of the wafer to ambient conditions, and keeping this wafer under vacuum. This technique permits the reliable use of inorganic or quasi- inorganic spin-on glasses in non batch type sputtering equipment.

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