Multi-port internally cached drams

Details Multi-port internally cached drams Multi-port internally cached drams

G - Physics

06

F

G06F 13/16 (2006.01)

Patent

CA 2297836

Apparatus for and method of enhancing the performance of multi-port internal cached DRAMs and the like by providing for communicating to system I/O resources messages sent by other such resources and the message location within the DRAM array, and further providing for efficient internal data bus usage in accommodating for both small and large units of data transfer.

L'invention porte sur un appareil et un procédé d'amélioration des performances d'une DRAM à plusieurs ports à antémémoire interne ou analogue consistant à communiquer au système des messages de ressources d'E/S fournis par d'autres telles ressources, ainsi que la localisation des messages à l'intérieur des circuits de la DRAM, tout en assurant une utilisation efficace du bus interne de données, de manière à pouvoir effectuer des transferts d'unités de données soit petites, soit importantes.

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