Multi-processor system

G - Physics – 06 – F

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354/234

G06F 13/00 (2006.01) G06F 12/02 (2006.01) G06F 12/06 (2006.01) G06F 13/28 (2006.01) G06F 13/42 (2006.01) G06F 15/16 (2006.01) G06F 15/167 (2006.01)

Patent

CA 1158779

MULTI PROCESSOR SYSTEM Abstract of the Disclosure There is disclosed a multi-processor system having a master processor and a plurality of slaves. Each processor is provided with its own memory. Although each slave proces- sor can access only its respective memory, the master proces- sor can access either its own memory or any one of the slave memories. Maximum throughput (efficiency) is achieved by suspend- ing operation of a single slave processor for only a single memory cycle, i.e., the time required for the master processor to access the respective slave memory. Each processor/memory is on a single card, with all of the cards being connected to a common bus. The cards are virtually identical, and master/slave distinctions are determined by a single slot bit on each card. A unique addressing scheme is implemented for access from the master to a selected slave.

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