G - Physics – 06 – F
Patent
G - Physics
06
F
G06F 9/46 (2006.01) G06F 12/08 (2006.01) G06F 15/16 (2006.01)
Patent
CA 2182841
In a multi-processor system including a plurality of processing units each having a cache memory, the processing units each include a synchronization counter for indicating a present synchronization state of the respective processing unit, and a cache state table for holding information regarding the respective entries of the cache memory. The cache state table includes a cache state and a cache synchronization count. The cache state holds the respective cache state used in a cache protocol. The cache synchronization count holds a value of the synchronization counter when an entry is loaded. The cache protocol in the multi-processor system is simplified to realize high-speed processing.
Corporation Nec
G. Ronald Bell & Associates
Yamazaki Takeshi
LandOfFree
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