Multi-processor system having a multi-port cache memory

Details Multi-processor system having a multi-port cache memory Multi-processor system having a multi-port cache memory

G - Physics

06

F

354/233, 354/241

G06F 12/08 (2006.01) G06F 13/20 (2006.01)

Patent

CA 1323110

ABSTRACT OF THE DISCLOSURE A multi-port cache memory of multi-port memory structure is connected to and shared with a plurality of processors. The multi-port cache memory may have two sets of interface signal lines, for instruc- tion fetch and for data read/write, to each processor. The multi-port cache memory may also be used only for data read/write. The system performance is further improved if a plurality of processors and a multi-port cache memory are fabricated on a single LSI chip.

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