Multi-speed logic analyzer

Details Multi-speed logic analyzer Multi-speed logic analyzer

G - Physics

06

F

354/46

G06F 1/04 (2006.01) G01R 31/3177 (2006.01) G06F 11/25 (2006.01) G06F 13/00 (2006.01) G11C 7/00 (2006.01)

Patent

CA 1172360

-13- Abstract A logic analyzer which can simultaneously measure one block of input data in detail and the same or another block of input data in rough form is dis- closed. The logic analyzer comprises first and second sections each including a memory circuit to store the input data and a word recognizer to detect the desired trigger word from the input data. These first and second sections receive different clocks having differ- ent rates, and the second memory circuit stores the first clock applied to said first section for recog- nizing the time relationship of these clock signals. A counter counts the first clock in accordance with the outputs from the first and second word recognizers for recognizing the time relationship of the first and second trigger words.

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