H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/136
H01L 23/52 (2006.01) H01L 21/31 (2006.01) H01L 21/48 (2006.01) H05K 3/18 (2006.01) H05K 3/14 (2006.01)
Patent
CA 1284692
Abstract: A method for fabricating a multilayer interconnection system that is fully planar with completely sealed and corrosion resistant conductors separated by dielectric material. The method involves forming a dielectric sub-layer overlying a base layer, the sub-layer being non-soluble after it is cured. A sacrificial sub-layer is then formed over the dielectric sub- layer, the sacrificial sub-layer being insoluble after it is cured. A portion of the sacrificial sub-layer is removed to expose a portion of the dielectric sub-layer. The exposed portion of the dielectric sub-layer and a selected portion surrounding the exposed portion is removed to expose a portion of the base layer with an exposed portion of the sacrificial sub- layer overhanging the exposed portion of the base layer. A first conductive adhesive sub-layer is deposited overlying the dielectric and sacrificial sub-layers and the exposed area of the base layer without overlaying the exposed overhanging portion facing the base layer of the sacrificial sub-layer. A conductive seeding sub-layer is deposited overlaying the first conductive adhesive sub-layer. The sacrificial sub-layer and the first conductive adhesive sub-layer and the conductive seeding sub- layer in contact with the sacrificial sub-layer are removed, a conductor sub-layer is formed by electrolessly plating a conductor sub-layer onto the seeding sub-layer, and then a second conductive adhesive sub-layer is formed by electrolessly plating the second adhesive sub-layer onto the conductor sub-layer to form a surface which is planar with the dielectric sub-layer. The resulting structures are useful, for example, as VLSI and ULSI devices.
566024
Digital Equipment Corporation
Kirby Eades Gale Baker
Wu Andrew L.
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