Multilevel cache system with graceful degradation capability

Details Multilevel cache system with graceful degradation capability Multilevel cache system with graceful degradation capability

G - Physics

06

F

354/224

G06F 11/10 (2006.01) G06F 12/12 (2006.01) G11C 29/00 (2006.01)

Patent

CA 1184665

ABSTRACT OF THE DISCLOSURE The directory and cache store of a multilevel set associative cache system are organized in levels of memory locations. Round robin replacement apparatus is used to identify in which one of the multilevels information is to be replaced. The directory includes parity detection apparatus for detecting errors in the addresses being written in the directory during a cache memory cycle of operation. Control apparatus combines such parity errors with signals indicative of directory hits to produce invalid hit detection signals. The control apparatus in response to the occurrence of a first invalid hit detec- tion signal conditions the round robin apparatus as well as other portions of the cache system to limit cache operation to those sections whose levels are error free whereby gracefully degrading cache operation.

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