Multilevel controller for a cache memory interface in a...

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06

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354/235, 354/230

G06F 12/02 (2006.01) G06F 9/22 (2006.01) G06F 12/08 (2006.01)

Patent

CA 1218162

- 26 - MULTMULTILEVEL CONTROLLER FOR A CACHE MEMORY INTERFACE IN A MULTIPROCESSING SYSTEM ABSTRACT OF TIRE INVENTION A two level controller has been described for a system interface between an auxiliary processor and main memory modules of a multiprocessing system which respective processor and system have different clock rates, memory access times and memory addressing capabilities.

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