Multilevel pwm inverter

H - Electricity – 02 – M

Patent

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321/54

H02M 1/12 (2006.01) H02M 7/155 (2006.01) H02M 7/48 (2006.01)

Patent

CA 1180051

TITLE MULTILEVEL PWM INVERTER INVENTORS Pradeep Bhagwat Victor R. Stefanovic ABSTRACT OF THE DISCLOSURE The multilevel inverter includes a voltage divider which when connected across a dc source ED, provides voltage at terminals having values between +ED to -ED. A first and a second set of thyristors pairs are connected between the positive or negative terminals, respect- ively, and a load terminal for applying selected voltage levels to the load. Any thyristor pair in these sets may be turned-off by firing the thyristor pair at the next highest voltage level. However, the main thyristors which are connected to the +ED or -ED terminal is turned- off by a commutation circuit. This circuit includes a single capacitor maintained at zero voltage and subjected to an oscillating voltage during the commutation cycle to turn-off the conducting main thyristor. Such an inverter can easily provide a waveform having a series of pulses at one or more voltage levels thereby eliminating harmonics in the output.

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