Multiloop phase-locked loop circuit

H - Electricity – 03 – L

Patent

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Details

H03L 7/18 (2006.01) H03L 7/087 (2006.01)

Patent

CA 2121390

PLL circuits which have both the merits of analog phase control, in which good C/N ratio can be realized, and the merits of digital phase control, in which broad-band lock can be performed. The PLL circuit includes a VCO for generating an output signal having a frequency which is variable in accordance with a control voltage; frequency-dividing means for frequency dividing the output signal of said VCO to obtain a feedback signal; reference-signal generating means for generating both a digital reference signal and an analog reference signal, each having a reference frequency first phase error-detecting means for comparing a phase of the feedback signal with a phase of the digital reference signal, to obtain a first phase error signal representing a phase error therebetween and integrating the first phase error signal; second phase error-detecting means for comparing the phase of the feedback signal with a phase of the analog reference signal, to obtain a second phase error signal representing a phase error therebetween, and adding the second phase error signal to the integrated first phase error signal to obtain a first composite phase error signal; third phase error-detecting means for comparing the phase of the feedback signal with the phase of the analog reference signal, to obtain a third phase error signal representing a phase error therebetween, and adding the third phase error signal to the first composite phase error signal to obtain a second composite phase error signal; and a low-pass filter for eliminating high-frequency components of the second composite phase error signal to obtain the control voltage for the VCO.

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