Multiphase frequency selective phase locked loop with...

Details Multiphase frequency selective phase locked loop with... Multiphase frequency selective phase locked loop with...

H - Electricity

03

L

328/10

H03L 7/08 (2006.01) H03B 27/00 (2006.01) H03L 7/087 (2006.01)

Patent

CA 1246156

27 52,149 ABSTRACT OF THE DISCLOSURE A circuit for providing a multiphase digitally synthesized sinusoidal output signal representative of a predetermined symmetrical component set of a multiphase source signal and having a predetermined phase relationship therewith is taught. The circuit comprises a phase compar- ator, a phase shifter and a synthesizer. The phase compar- ator produces an output representative of the phase error in the predetermined phase relationship between the source signal and the output signal. The phase shifter has a variable frequency output for shifting the phase of the synthesized output signal in response to the phase error output signal of the phase comparator. The synthesizer digitally synthesizes at a predetermined amplitude the multiphase sinusoidal output signal. The synthesizer is responsive to the phase shifting output of the phase shifter so as to decrease the phase error between the source signal and output signal. When the phase error has been reduced to substantially a zero value, the output of the synthesizer will lock into a predetermined phase relationship with the source signal. The synthesized output signal can be in phase or in quadrature with the source signal. Either the positive or negative sequence set of the multiphase source signal can be used. In an alternate embodiment, a second synthesizer is provided for producing a second multiphase synthesized output signal that is in quadrature with the first multiphase synthesized output signal that is in phase with the positive sequence set of the multiphase source signal.

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