Multiple buffer computer display controller apparatus

Details Multiple buffer computer display controller apparatus Multiple buffer computer display controller apparatus

G - Physics

09

G

G09G 5/36 (2006.01) G09G 5/391 (2006.01) G09G 5/399 (2006.01)

Patent

CA 2085233

2085233 9120073 PCTABS00008 Multiple buffers are employed in a display controller for a computer display system. A video RAM is utilized in the display controller to hold display data corresponding to graphics to be displayed on the computer display monitor. And a series of dynamic RAMs are employed in the display controller to hold display data corresponding to images to be displayed on the computer display monitor. A data mixer receives and mixes signals from the video RAM and one of the dynamic RAMs to form signals which are used to drive the display monitor. The signals provide graphics displayed at one resolution overlaid on images displayed at a different resolution on the monitor. A FIFO buffer and rectangle loader provide efficient loading of blocks of display data in the display controller buffers.

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