G - Physics – 06 – F
Patent
G - Physics
06
F
354/233
G06F 15/16 (2006.01) G06F 15/173 (2006.01)
Patent
CA 2036688
A signal processor architecture that comprises a data network having multiple ports, a control bus, and a plurality of signal processing clusters connected to at least two ports and the control bus. Each signal processing cluster comprises a systemcontrol processor connected to the control bus, a second control bus, and a global bulk memory having multiple ports. A plurality of functional processing elementsare connected to the system control processor by way of the second control bus, and each are connected to a port of the global bulk memory. The global bulk memory comprises a subdata flow network having multiple gateways and full crossbar inter- connectivity between each of the multiple gateways. The data network and subdataflow network allow data to be transferred between functional processing elements in the signal processing cluster and any functional processing element and global bulk memory in another signal processing cluster, and allow data to be transferred from any functional processing element into and out of the processor architecture. The first control bus is arbitrated for access on a message by message basis and the data network is arbitrated on a message by message basis for transfers between ports.This results in a relatively loose coupling between the signal processing clusters. The second control bus is arbitrated for access on a word by word basis and the global bulk memory is arbitrated for port access on each global bulk memory cycle. Thisresults in tight coupling within each signal processing cluster.
Benedict Douglas M.
Tower Lee W.
Wagner Jeffrey A.
Hughes Aircraft Company
Sim & Mcburney
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