Multiple cpu control system

Details Multiple cpu control system Multiple cpu control system

G - Physics

06

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340/84

G06F 15/00 (2006.01) G06F 13/36 (2006.01) G06F 13/40 (2006.01) G06F 13/42 (2006.01)

Patent

CA 1129516

-1- MULTIPLE CPU CONTROL SYSTEM ABSTRACT OF THE DISCLOSURE A logic system in an intersystem link (ISL) unit is provided for avoiding deadlock conditions which may occur in a data processing system wherein multiple CPUs on one communication bus attempt to communicate with resources on remote communication busses. The data processing system has plural communication busses, each providing a common information path to plural data processing units including memory units, peripheral control units, central processing units (CPUs) and ISL units, and each of the plural communication busses are in electrical communication with an ISL unit, and ISL units are electrically connected in pairs.

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