Multiple data path cpu architecture

Details Multiple data path cpu architecture Multiple data path cpu architecture

G - Physics

06

F

354/166, 354/221

G06F 9/38 (2006.01) G06F 13/38 (2006.01)

Patent

CA 1215783

ABSTRACT The various functional units which comprise a central processing unit of a computer are organized so as to enable a main arithmetic logic unit and special function units including an auxilliary arithmetic logic unit to access data registers, literal constants, and data from a memory cache. A general purpose bus closely couples the functional units to the main data paths and allows the CPU sequencer to branch on numerous conditions which may be indicated via test lines. Parity from the functional units is sent a clock cycle later than results in order that the parity path does not affect machine cycle time. The architecture allows unused microcode options to be used to check for correct CPU operation by halting CPU operation on a miscompare of two buses.

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