Multiple execution unit dispatch with instruction dependency

Details Multiple execution unit dispatch with instruction dependency Multiple execution unit dispatch with instruction dependency

G - Physics

06

F

G06F 15/16 (2006.01) G06F 9/38 (2006.01)

Patent

CA 2123442

MULTIPLE EXECUTION UNIT DISPATCH WITH INSTRUCTION DEPENDENCY Abstract A multiple execution unit processing system is provided wherein each execution unit has an associated instruction buffer and all instruction are executed in order. The first execution unit (unit 0) will always contain the oldest instruction and the second unit (unit 1) the newest. Processor instructions, such as load, store, add and the like are provided to each of the instruction buffers (0,1) from an instruction cache buffer. The first instruction (oldest) is placed in buffer 0 and the next (second) instruction is stored in buffer 1. It is determined during the decode stage whether the instructions are dependent on an immediately preceding instruction. If both instructions are independent of other instructions, then they can execute in parallel. However, if the second instruction is dependent on the first, then (subsequent to the first instruction being executed) it is laterally shifted to the first instruction buffer. Instructions are also defined as being dependent on an unavailable resource. In most cases these "unavailable" instructions are allowed to executed in parallel on the execution units.

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