Multiple match detection circuit and method

Details Multiple match detection circuit and method Multiple match detection circuit and method

G - Physics

01

R

G01R 19/155 (2006.01) G11C 11/56 (2006.01) G11C 15/00 (2006.01) G11C 15/04 (2006.01)

Patent

CA 2310295

A multiple matchline sense circuit for detecting a single, more than one, or no match conditions during a search-and-compare operation of a content addressable memory is disclosed. The circuit compares the rising voltage rate of a multiple matchline to the rising voltage rate of a reference multiple matchline in order to generate a multibit result representing one of the three conditions. The circuit generates a self-timed control signal to end the search-and-compare operation, and to set the circuit to a precharge state.

Circuit de détection de concordances multiples permettant de détecter une concordance, plusieurs concordances ou une absence de concordance en exécutant une opération de recherche et de comparaison d'un contenu de mémoire adressable. Le circuit compare le taux d'augmentation de la tension de plusieurs lignes de concordance au taux d'augmentation de la tension de plusieurs lignes de concordance de référence afin de générer un résultat multibits représentant une des trois conditions précitées. Le circuit génère un signal de contrôle autotemporisé pour mettre fin à l'opération de recherche et de comparaison et effectuer un réglage en fonction d'un taux de préchargement.

Affiliated with

Also associated with

Rating

Multiple match detection circuit and method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multiple match detection circuit and method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiple match detection circuit and method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1720893