Multiple-processing and contamination-free plasma etching...

H - Electricity – 01 – J

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204/167.3

H01J 37/18 (2006.01) C23F 4/00 (2006.01) H01J 37/20 (2006.01) H01J 37/32 (2006.01) H01L 21/00 (2006.01)

Patent

CA 1331163

ABSTRACT The present invention includes plural plasma etching vessels and a wafer queuing station arrayed with a wafer transfer arm in a controlled environment. Wafers are movable within the controlled environment one at a time selectably between the several plasma vessels and the wafer queuing station without atmospheric or other exposure so that possible contamination of the moved wafersis prevented. The system is selectively operative in either single-step or multiple- step processing modes, and in either of the modes, the several plasma etching vessels are operable to provide a desirably high system throughput. In the preferred embodiment, the several plasma vessels and the queuing station are arrayed about a closed pentagonal locus with the wafer transfer arm disposed within the closed locus. The wafer transfer arm is movable in R and TT between the several plasma etching vessels and the wafer queuing station, and selectablyactuatable vacuum locks are provided between each of the plasma etching vessels and the R and TT movable wafer transfer arm to both maintain an intended atmospheric condition and to allow wafer transport therethrough. The plasma vessels each include first and second water-cooled electrodes that are movable relatively to each other so as to provide a selectable gap dimension therebetween. One of the electrodes includes a selectively movable pedestal portion slidably mounted thereto that is cooperative with the R and TT movable wafer transfer armto load and unload wafers respectively into and out of the associated plasma vessel. The wafer transfer arm is operative to pick-up the wafers by back-side and peripheral wafer contact only, which therewith prevents possible front-side contact-induced contamination of the wafer surfaces. A sensor on the transfer arm is operative to provide a signal indication of proper wafer seating. - 1 -

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