Multiple processor communications system

Details Multiple processor communications system Multiple processor communications system

G - Physics

06

F

354/230.7

G06F 19/00 (2006.01) G05B 19/05 (2006.01)

Patent

CA 1337876

A multiple processor communications system including a control processor and a scan processor having its own program counter enabling the efficient execution of sub-routines. The scan processor directly accesses a compiled user memory which contains its operating program and also directly accesses the image memory which contains the input and output data to perform the computations required by the program. The system includes error codes for distinguishing various error conditions including collision error conditions indicating illegal commands to the scan processor when it is scanning and parity errors in the compiled user memory and in the image memory.

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