Multiple source clock encoded communications error detection...

Details Multiple source clock encoded communications error detection... Multiple source clock encoded communications error detection...

H - Electricity

04

L

340/74

H04L 7/00 (2006.01) H04L 1/00 (2006.01)

Patent

CA 1187958

MULTIPLE SOURCE CLOCK ENCODED COMMUNICATIONS ERROR DETECTION CIRCUIT Abstract of the Disclosure This invention relates to an error detection circuit for detecting errors in a recovered clock signal from a self-clocking digital data signal. A first flip- flop is alternately set and reset by the recovered clock signal and by a clock source of supposedly equal fre- quency, respectively. The output of the first flip-flop is sensed by a second flip-flop at the end of a pre- determined time period, as determined by the clock source, for determining that a transition in the re- covered clock source occurred within the predetermined time period. If no transition occurred within the predetermined time period, the second flip-flop outputs an error signal.

411862

Affiliated with

Also associated with

Rating

Multiple source clock encoded communications error detection... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multiple source clock encoded communications error detection..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiple source clock encoded communications error detection... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1299067