Multiplex bus system

Details Multiplex bus system Multiplex bus system

H - Electricity

04

J

363/17

H04J 3/06 (2006.01) H04L 12/40 (2006.01) H04Q 9/14 (2006.01) B60R 16/02 (2006.01) H04L 7/06 (2006.01)

Patent

CA 1213084

Abstract A multiplex bus system (Fig. 1) comprises a master control unit (MCU) (12) connected to at least one receiver-transmit unit (RTU) (16, Fig. 3) by a data bus (14). The MCU transmits to the RTU a message (Fig. 5) comprising a synchronization pulse (SYNC') of known duration (2 2/3 T). The message also includes successive, time-spaced level transitions, which are separated from each other by time duration T. The transitions mark respective boundaries of data bits within each message. The RTU includes a clock pulse source (81, R, C), which utilizes the synchronization pulse of each message to determine the number, P, of second clock pulse source pulses per duration T. The number, P, is used in conjunction with the level transition signals in the message to mark in the RTU the positions of additional transitions, which additional transitions are positioned within data bit positions of the message to indicate values of respective data bits.

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