G - Physics – 11 – C
Patent
G - Physics
11
C
354/237
G11C 8/00 (2006.01) G06F 12/02 (2006.01) G06F 13/00 (2006.01)
Patent
CA 1212481
- 19 - MULTIPLEXED-ADDRESS INTERFACE FOR ADDRESSING MEMORIES OF VARIOUS SIZES Abstract Disclosed is a computer system (FIG. 1) that is operable with any multiplexed-address memory within a size range of 2N to 2N+R memory locations. The system has a memory of 2S locations selected from the predetermined range, and the memory has ? multiplexed address input terminals. Address bits forming a memory address, generated for example by a processor, are multiplexed by a memory controller onto ?+R address output terminals in two sets of ?+R address bits. The address bit sets have at least ? bits in common. An address bus transports the multiplexed address bits to the memory. The bus has ?+R address leads connected to the output terminals of the memory controller. ? of those address leads are also connected to the address input terminals of the memory. The remaining address leads are not connected. The memory controller multiplexes the address of any memory within the predetermined range onto its output terminals. Addressing of a different-size memory requires merely connecting the memory to the appropirate address leads of the multiplexed-address bus. (FIG. 1)
457643
Grinn James M.
Mcwethy Kevin A.
Kirby Eades Gale Baker
Ncr Corporation
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