Multiplexed memory timing with block reset and secondary memory

Details Multiplexed memory timing with block reset and secondary memory Multiplexed memory timing with block reset and secondary memory

G - Physics

09

G

G09G 3/34 (2006.01) G02B 27/00 (2006.01)

Patent

CA 2149930

A spatial light modulator array with adaptable multiplexed memory architecture. The modulator has an array of individually controllable pixels, where a predetermined number of pixels are assigned to a memory cell (16). The memory cell receives data from an input bus (14). On a signal (22), the memory cell transfers its data to a secondary memory (18), and to the activation circuitry (20) of one of its assigned pixels. On a second signal, the pixel responds to the data on the activation circuitry. When the display time of the data is less than the load time for the memory cell, the secondary memory is set with a second signal (24) so as to make the pixel dark and another control signal makes the pixels respond to the memory. In this way, the load time is lengthened and the data rate remains relatively low, even though the number of bits of intensity may not be the same as the number of bits of intensity used to determine the number of pixels assigned to each memory cell.

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