Multiplexed operation of write enable terminal of a memory...

Details Multiplexed operation of write enable terminal of a memory... Multiplexed operation of write enable terminal of a memory...

G - Physics

11

C

352/81

G11C 11/34 (2006.01) G11C 5/14 (2006.01)

Patent

CA 1162647

MULTIPLEXED OPERATION OF WRITE ENABLE TERMINAL OF A MEMORY CIRCUIT FOR CONTROL AND BACKUP POWER FUNCTIONS ABSTRACT OF TIE DISCLOSURE A computer system (10) includes a memory (28) which receives primary power from a power supply (24). A control circuit (14) generates a write enable signal which is provided to a first input line (16) of a switch (58). A secondary power source (54) provides backup power through a line (56) to the switch (58). The power supply (24) generates a primary power warning signal on a line 62 which is connected to control the operation of switch (58). The output line (60) of the switch (58) is connected to each of the write enable terminals of memory circuits (30-44) in the memory (28). Upon detection of failure of the primary power for the computer (10), the switch (58) is activated to disconnect the write enable signal on the input line (16) from the output line (60) of switch (58). The switch (58) is further caused to connect line (56) of the secondary power source (54) to the output line (60) of switch (58) to supply backup power to each of the memory circuits (30-44) in the memory (28).

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