Multiplexed psk demodulator

Details Multiplexed psk demodulator Multiplexed psk demodulator

H - Electricity

03

D

329/3, 331/35

H03D 3/22 (2006.01) H04L 27/227 (2006.01)

Patent

CA 1257662

"MULTIPLEXED PSR DEMODULATOR" Abstract An improved quadrature differential phase shift keyed signal demodulator for use in a modem is shown. A delay circuit (12) delays an input signal for a portion of a baud time. Synchronous detectors (21, 23) mix the original and delayed input signals with coherent reference signals to obtain detected outputs which are alternately provided to a processor (60) by a multiplexer (25). The processor (60) determines the phase shift and provides the demodulated data. An offset baud clock phase locked loop (40) provides a baud clock which is offset by a ninety degree phase lag. The offset baud clock causes the multiplexer (25) to provide detected outputs to the processor (60) for the center one-half of each baud. The result is a demodulator with fewer components and an improved data error rate.

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