Multiplexed serial register architecture for vram

Details Multiplexed serial register architecture for vram Multiplexed serial register architecture for vram

G - Physics

11

C

352/82.4

G11C 11/40 (2006.01) G11C 11/34 (2006.01) G11C 11/409 (2006.01) G11C 11/4096 (2006.01)

Patent

CA 2026461

Abstract of the Disclosure MULTIPLEXED SERIAL REGISTER ARCHITECTURE FOR VRAM A dual-port DRAM in which a single serial latch is shared between two pairs of folded bit lines from two arrays of memory cells. A first set of mux devices selects one of the two pairs of folded bit lines from each of the arrays, and a second set of mux devices selectively couple one of the remaining folded bit line pairs to either the parallel port or the serial latch for access to the serial port. This arrangement greatly decreases the consumption of chip real estate. At the same time, it makes unlimited vertical scrolling possible through the use of a copy mode that can be carried out in two operating cycles, and facilitates masked writing, while at the same time reducing clocking complexity.

Affiliated with

Also associated with

Rating

Multiplexed serial register architecture for vram does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Multiplexed serial register architecture for vram, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Multiplexed serial register architecture for vram will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1407220