H - Electricity
04
J
363/17
H04J 3/04 (2006.01)
Patent
CA 1266535
Abstract of the Disclosure A multiplexer includes first and second frequency dividers and first and second selectors. The first frequency divider receives a clock signal which determines a multiplexing time slot and outputs a first signal every M (M ? 2) time slots. The second frequency divider receives the first signal from said first frequency divider and outputs N (N ? 1) second signals having different phases. The first selector converts N insertion codes such as a frame synchronization code and a service code into one code signal train on the basis of the second signals. The second selector receives a digital data signal train having an alternate repetition of a digital data signal using (M - 1) continuous time slots and a gap of one time slot and inserts the insertion codes of the code signal train on the basis of the first signal.
542477
Corporation Nec
Smart & Biggar
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