Multiplier

Details Multiplier Multiplier

G - Physics

06

F

354/167

G06F 7/52 (2006.01) G06F 7/48 (2006.01)

Patent

CA 2007054

MULTIPLIER ABSTRACT A multiplier which processes 32 bit operands to provide two 16 bit by 16 bit fixed point products or one 32 bit floating point product during each clock pulse. Two 16 bit by 16 bit fixed point products or one 32 bit floating point product arc ini- tiated on every clock pulse and results of the multiplication process are available after a fixed pipeline delay on a continuous basis. The fixed and floating point pipe- line operations may also be interleaved. The 32 bit input operands are selected from three external sources or from the last output product. A modified Booth algorithm is implemented employing dual parallel processing paths which are employed to sepa-rately produce the 16 bit by 16 bit fixed point products or are combined to produce the 32 bit floating point product. Exponent computations are performed in parallel h the floating point computational mode.

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