Multiprocessor controller having shared control store

Details Multiprocessor controller having shared control store Multiprocessor controller having shared control store

G - Physics

06

F

354/230.7

G06F 9/22 (2006.01) G06F 13/12 (2006.01)

Patent

CA 2007004

MULTIPROCESSOR CONTROLLER HAVING SHARED CONTROL STORE Abstract of the Disclosure A controller connected between a system bus and peripheral devices has at least two microprocessors. One controls the data transfers with the peripheral devices, and the other controls data transfers with the system bus. The microprocessors share a data buffer and control store. This sharing is possible because of the controller timing means which synchronizes exclusive access to the shared com- ponents of the controller. When first initialized, the microprocessors are directed to execute a test instruction which points them to the beginning of their set of microinstructions. Once pointed to their set of microinstructions, normal operation may begin.

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